In an ideal memory system, memory components commanded to transmit data one after another on a shared signaling link will output data in respective burst intervals seamlessly and without contention, the output driver in one component being disabled just as the output driver in the other is enabled. In practice, however, various sources of timing skew may result in brief overlap between driver-enable intervals within the two memory components and thus a transitory interval of simultaneous transmission on the shared signaling link referred to herein as “link contention.” Such link contention is particularly problematic when push-pull output drivers are simultaneously enabled to drive the signaling link to opposite states, as high and low voltage nodes of the signaling power supply are briefly shorted to one another, consuming power and injecting noise.
Although delays or “bubbles” may be inserted between burst intervals to avoid link contention, such delays increase overall memory latency and reduce the effective bandwidth of the signaling link, a performance penalty multiplied by the number of signaling links. Also, the relatively coarse timing granularity of the delay control source (e.g., the core domain of a memory controller) may impose a delay interval many times longer than needed to avoid signaling contention, thus magnifying the performance penalty.